1. Technical Field
The present invention relates to microprocessors and, in particular, to mechanisms for resetting the machine states of processors.
2. Background Art
Reset refers to the mechanism by which a computer system is put into a reference state. A computer system may be reset when it is first turned on, or an operating computer system may be reset in response to events, such as the occurrence of certain error conditions. At reset, the central processing unit (CPU or processor) of the computer system is typically put into a particular machine state. For a computer system that does not support functional redundancy checking (FRC), this state may be defined “loosely”. For example, a reset pin may force a relatively small fraction of the processor nodes, e.g. latches, flip flops and the like, to specified logic states, with the states of the remaining nodes left indeterminate. For such non-FRC systems, the indeterminate states of the unspecified nodes have no impact on the visible results produced by the processor at its output pins. Such processors may be more difficult to debug, but the problem is still relatively manageable.
For processors that implement FRC, the reset state can have a significant impact on debug, verification and operation. One mechanism for implementing FRC replicates the instruction execution cores of a processor, runs the same instruction code on each processor core and compares results from the different cores at one or more stages of execution. If a discrepancy is detected, the computer system enters an error-handling mode, which may require reset of one or both pipelines. Current processing technologies allow the replicated cores to be implemented on a single processor die (multi-core processors).
The points of comparison between results from the different execution cores form the FRC boundary. The FRC boundary typically includes many more signals than appear on the processor's input/output (I/O) pins to provide reliable checking. The machine states of a processor that implements FRC are thus examined at a significantly finer level of detail than those of a non-FRC processor. Indeterminate states in the nodes of one or the other execution core can lead to unnecessary mismatches at the FRC boundary.
One strategy for addressing this problem is to run a reset code module in response to a reset event. The reset code steps the processor through a precise sequence of operations that force targeted processor nodes to specified logic states. More nodes may be driven to specified states by using ever larger and more complex reset codes, but developing, debugging and validating such reset codes is very costly.
The present invention address these and other problems associated with generating deterministic reset states for processors.